| 000 | 01173cam a2200313 a 4500 | ||
|---|---|---|---|
| 001 | 2599831 | ||
| 005 | 20240801140703.0 | ||
| 008 | 970924s1998 maua b 001 0 eng | ||
| 010 | _a 97042061 | ||
| 020 | _a0792380797 | ||
| 040 |
_aDLC _cDLC _dDLC |
||
| 050 | 0 | 0 |
_aTK7874.65 _b.S58 1998 |
| 082 | 0 | 0 |
_a621.39/5/0287 _221 |
| 100 | 1 |
_aSivaraman, Mukund, _d1970- _91144 |
|
| 245 | 1 | 2 |
_aA unified approach for timing verification and delay fault testing / _cMukund Sivaraman and Andrzej J. Strojwas |
| 260 |
_aBoston: _bKluwer Academic, _c1998 |
||
| 300 |
_axv, 155 p.: _bill. ; _c25 cm. |
||
| 504 | _aIncludes bibliographical references and index. | ||
| 650 | 0 |
_aDigital integrated circuits _91145 |
|
| 650 | 0 |
_aDigital integrated circuits _91146 |
|
| 650 | 0 |
_aDelay faults _91147 |
|
| 650 | 0 |
_aIntegrated circuits _xVerification. _91148 |
|
| 700 | 1 |
_aStrojwas, Andrzej J. _91149 |
|
| 856 | 4 | 2 | _3Publisher description |
| 856 | 4 | 1 | _3Table of contents only |
| 906 |
_a7 _bcbc _corignew _d1 _eocip _f19 _gy-gencatlg |
||
| 942 |
_2lcc _cBK |
||
| 999 |
_c3745 _d3745 |
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